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6.07 january 2009 dsc-5668/2 1 ?2009 integrated device technology, inc. i/o control address decoder memory array arbitration interrupt semaphore logic address decoder i/o control r/ w l ce l oe l busy l a 13l (1) a 0l 5668 drw 01 i/o 0l -i/o 7l ce l oe l r/ w l sem l int l m/ s busy r i/o 0r -i/o 7r a 13r (1) a 0r sem r int r ce r oe r (3) (2,3) (2,3) (3) r/ w r ce r oe r 14 14 r/ w r , high-speed 2.5v 16/8k x 8 dual-port static ram features true dual-ported memory cells which allow simultaneous reads of the same memory location high-speed access ? commercial: 20/25ns (max.) ? industrial: 25ns (max.) low-power operation ? idt70t06/5l active: 200mw (typ.) standby: 600w (typ.) idt70t06/5 easily expands data bus width to 16 bits or more using the master/slave select when cascading more than one device interrupt flag m/ s = v ih for busy output flag on master m/ s = v il for busy input on slave on-chip port arbitration logic full on-chip hardware support of semaphore signaling between ports fully asynchronous operation from either port battery backup operation?2v data retention lvttl-compatible, single 2.5v (100mv) power supply available in a 64-pin tqfp and 100-pin fp bga industrial temperature range (-40c to +85c) is available for selected speeds functional block diagram notes: 1. a 13 is a nc for idt70t05. 2. (master): busy is output; (slave): busy is input. 3. busy outputs and int outputs are non-tri-stated push-pull. preliminary idt70t06/5l
2 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges preliminary description the idt70t06/5 is a high-speed 16/8k x 8 dual-port static ram. the idt70t06/5 is designed to be used as a stand-alone 128k-bit dual-port static ram or as a combination master/slave dual-port static ram for 16-bit-or-more word systems. using the idt master/slave dual- port static ram approach in 16-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. this device provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature controlled by ce permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using idt?s cmos high-performance technology, these devices typically operate on only 200mw of power. the idt70t06/5 is packaged in a 64-pin thin quad flatpack and 100-pin fine pitch ball grd array. pin configurations (1,2,3,4) notes: 1. a 13 is a nc for idt70t05. 2. all v dd pins must be connected to power supply. 3. all v ss pins must be connected to ground supply. 4. pn-64 package body is approximately 14mm x 14mm x 1.4mm. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part marking. i ndex 70t06/5pf pn-64 (5) 64-pin tqfp top view (6) 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 46 45 44 43 42 41 40 39 38 37 36 35 34 47 48 33 1 7 1 8 1 9 2 0 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 4 9 5 0 5 1 5 2 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 6 4 i/o 2l v dd v ss v ss a 4r busy l busy r int r int l v ss m/ s o e l a 5 l i / o 1 l r / w l c e l s e m l v d d o e r c e r r / w r s e m r a 1 2 r v s s i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l i/o 0r i/o 1r i/o 2r v dd i/o 3r i/o 4r i/o 5r i / o 6 r i / o 7 r a 1 1 r a 1 0 r a 9 r a 8 r a 7 r a 6 r a 5 r a 3r a 2r a 1r a 0r a 0l a 1l a 2l a 3l a 4l a 6 l a 7 l a 8 l a 9 l a 1 0 l a 1 1 l a 1 2 l i / o 0 l 5668 drw 02 a 1 3 r ( 1 ) a 1 3 l ( 1 ) , 08/14/02
6.42 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges 3 preliminary notes: 1. a 13 is a nc for idt70t05. 2. all v dd pins must be connected to power supply. 3. all v ss pins must be connected to ground supply. 4. package body is approximately 1.18 in x 1.18 in x .16 in. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part marking. pin configurations (1,2,3,4) (con't.) c10 i/o 3r d8 nc c8 nc a9 nc d9 i/o 5r c9 nc b9 nc d10 i/o 1r c7 ce r b8 oe r a8 r/ w r a10 i/o 7r d7 sem r b7 a7 nc b6 nc c6 nc d6 nc a5 v ss b5 nc c5 nc d5 a 11r a4 nc b4 a 10r c4 a 7r d4 nc a3 a 12r b3 a 8r c3 a 5r d3 a 2r d2 int r c2 a 4r b2 nc a2 a 9r a1 a 6r b1 nc c1 a 3r d1 a 1r e1 m/ s e2 busy r e3 a 0r e4 a 1l f1 v ss f2 busy l f3 a 0l f4 nc g1 int l g2 a 3l g3 a 6l g4 nc h1 a 2l h2 a 5l h3 a 10l h4 nc j1 a 4l j2 a 8l j3 a 11l j4 nc k1 a 7l k2 a 9l k3 a 12l k4 nc a6 v ss b10 i/o 6r e5 v ss e6 v ss e7 i/o 4r e8 i/o 2r e9 i/o 0r e10 v dd f5 v dd f6 v ss f8 i/o 5l f9 i/o 6l f10 i/o 7l g5 nc g6 sem l g7 nc g8 i/o 3l g9 v ss g10 i/o 4l h5 nc h6 ce l h7 nc h8 nc h9 nc h10 i/o 2l j5 nc j6 j7 r/ w l j8 nc j9 v ss j10 i/o 1l k5 v dd k6 v dd k7 nc k8 nc k9 oe l k10 i/o 0l f7 v dd 5668 drw 03 a 13l (1) a 13r (1) 08/14/02 idt70t06/5bf bf100 (5) 100-pin fpbga top view (6)
4 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges preliminary left port right port names ce l ce r chip enable r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 13 l (1 ) a 0r - a 13r (1) address i/o 0l - i/o 7l i/o 0r - i/o 7r data input/output sem l sem r semaphore enable int l int r interrupt flag busy l busy r busy flag m/ s master or slave select v dd power (2.5v) v ss ground (0v) 5668 tbl 01 truth table i: non-contention read/write control truth table ii: semaphore read/write control (1) note: 1. a 0l ? a 13l a 0r ? a 13r note: 1. there are eight semaphore flags written to via i/o 0 and read from i/o 0 - i/o 7 . these eight semaphores are addressed by a 0 - a 2 . inputs (1 ) outputs mode ce r / w oe sem i/o 0-7 h x x h high-z deselected: power-down llxhdata in write to memory lhlhdata out read memory x x h x high-z outputs disabled 5668 tbl 02 inputs outputs mode ce r/ w oe sem i/o 0-7 hhl ldata out read data in semaphore flag h xldata in write i/o 0 into semaphore flag lxxl ____ not allo wed 5668 tbl 03 pin names note: 1. a 13 is a nc for idt70t05.
6.42 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges 5 preliminary recommended dc operating conditions maximum operating temperature and supply voltage (1) absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v dd + 0.3v. note: 1. this is the parameter t a . this is the "instant on" case temperature. notes: 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed v dd +0.3v. symbol rating commercial & industrial unit v term (2 ) terminal voltage with re sp ect to gnd -0.5 to +3.6 v t bias (3 ) temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn junction temperature +150 o c i out dc output current 50 ma 5668 tbl 04 grade ambient temperature gnd v dd commercial 0 o c to +70 o c0v2.5v + 100mv industrial -40 o c to +85 o c0v2.5v + 100mv 5668 tbl 05 symbol parameter min. typ. max. unit v dd supply voltage 2.4 2.5 2.6 v v ss ground 0 0 0 v v ih input high voltage 1.7 ____ v dd +0.3 (2 ) v v il input low voltage -0.3 (1 ) ____ 0.7 v 5668 tbl 06 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 2.5v 100mv) symbol parameter test conditions 70t06/5l unit min. max. |i li | input leakage current (1 ) v dd = 2.6v, v in = 0 v to v dd ___ 5a |i lo | output leakage current v out = 0v to v dd ___ 5a v ol output low voltage i ol = +2ma ___ 0.4 v v oh output high voltage i oh = -2ma 2.0 ___ v 5668 tbl 08 note: 1. at v dd < 2.0v input leakages are undefined. capacitance (t a = +25c, f = 1.0mhz) notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0v to 3v or from 3v to 0v. symbol parameter (1 ) conditions max. unit c in input capacitance v in = 3dv 9 pf c out output capacitance v out = 3dv 10 pf 5668 tbl 07 3. ambient temperature under bias. no ac conditions. chip deselected.
6 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges preliminary timing of power-up power-down ce 5668 drw 05 t pu i cc i sb t pd , dc electrical characteristics over the operating temperature and supply voltage range (v dd = 2.5v 100mv) 70t06/5l20 com'l only 70t06/5l25 com'l & ind symbol parameter test condition version typ. (2 ) max. typ. (2) max. unit i dd dynamic operating current (both ports active) ce = v il , outputs disabled sem = v ih f = f max (3) com'l l 80 140 70 130 ma ind l ____ ____ 100 160 i sb1 standby current (both ports - ttl level inp uts) ce r and ce l = v ih sem r = sem l = v ih f = f max (3) com'l l 12 20 7 17 ma ind l ____ ____ 12 25 i sb2 standby current (one po rt - ttl level inp uts) ce "a" = v il and ce "b" = v ih (1) active port outputs disabled, f=f max (3) sem r = sem l = v ih com'l l55904080 ma ind l ____ ---- 55 100 i sb3 full standby current (both ports - cmos level inp uts) both ports ce l and ce r > v dd - 0.2v, v in > v dd - 0.2v or v in < 0.2v, f = 0 (4 ) sem r = sem l > v dd -0.2v com'l l 0.05 2.5 0.05 2.5 ma ind l ____ ____ 0.2 5.0 i sb4 full standby current (one port - cmos level inp uts) ce "a" < 0.2v and ce "b" > v dd - 0.2v (1 ) sem r = sem l > v dd -0.2v v in > v dd - 0.2v or v in < 0.2v active port outputs disabled, f = f max (3) com'l l55904080 ma ind l ____ ____ 55 100 5668 tbl 09 notes: 1. port "a" may be either left or right port. port "b" is the opposite from port "a". 2. v dd = 2.5v, t a = +25c, and are not production tested. i dd dc = 85ma (typ.) 3. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc , and using ?ac test conditions? of input levels of gnd to 3v. 4. f = 0 means no address or control lines change. input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 2.5v 3ns max. 1.25v 1.25v figure 1 5668 tbl 10 ac test conditions 1.25v 50 ? 50 ? 5668 drw 04 10pf / 5pf* (tester) d ata out , busy int figure 1. ac output test load *(for t lz , t hz , t wz , t ow )
6.42 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges 7 preliminary notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . ac electrical characteristics over the operating temperature and supply voltage range 70t06/5l20 com'l only 70t06/5l25 com'l & ind unit symbol parameter min. max. min. max. read cycle t rc read cycle time 20 ____ 25 ____ ns t aa address access time ____ 20 ____ 25 ns t ace chip enable access time (3 ) ____ 20 ____ 25 ns t abe byte enable access time (3 ) ____ 20 ____ 25 ns t aoe output enable access time (3 ) ____ 12 ____ 13 ns t oh output hold from address change 3 ____ 3 ____ ns t lz output low-z time (1,2) 3 ____ 3 ____ ns t hz output high-z time (1,2) ____ 12 ____ 15 ns t pu chip enable to power up time (1,2) 0 ____ 0 ____ ns t pd chip disable to power down time (1,2) ____ 20 ____ 25 ns t sop semaphore flag update pulse ( oe or sem )10 ____ 10 ____ ns t saa semaphore address access (3) ____ 20 ____ 25 ns 5668 tbl 1 1 waveform of read cycles (5) notes: 1. timing depends on which signal is asserted last oe or ce . 2. timing depends on which signal is de-asserted first ce or oe . 3. t bdd delay is required only in cases where the opposite port is completing a write operation to the same address location. for simul taneous read operations busy has no relation to valid output data. 4. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa or t bdd . 5. sem = v ih . t rc r/ w ce addr t aa oe 5668 drw 06 (4) t ace (4) t aoe (4) (1) t lz t oh (2) t hz (3,4) t bdd data out busy out valid data (4)
8 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges preliminary ac electrical characteristics over the operating temperature and supply voltage symbol parameter 70t06/5l20 com'l only 70t06/5l25 com'l & ind unit min. max. min. max. write cycle t wc write cycle time 20 ____ 25 ____ ns t ew chip enable to end-of-write (3) 15 ____ 20 ____ ns t aw address valid to end-of-write 15 ____ 20 ____ ns t as address set-up time (3) 0 ____ 0 ____ ns t wp write pulse width 15 ____ 20 ____ ns t wr write recovery time 0 ____ 0 ____ ns t dw data valid to end-of-write 15 ____ 15 ____ ns t hz output high-z time (1,2) ____ 12 ____ 15 ns t dh data hold time (4 ) 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 12 ____ 15 ns t ow output active from end-of-write (1, 2,4) 0 ____ 0 ____ ns t swrd sem flag write to read time 5 ____ 5 ____ ns t sp s sem flag contention window 5 ____ 5 ____ ns 5668 tbl 12 notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 1). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access sram, ce = v il , sem = v ih . to access semaphore, ce = v ih and sem = v il . either condition must be valid for the entire t ew time. 4. the specification for t dh must be met by the device supplying write data to the sram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow .
6.42 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges 9 preliminary timing waveform of write cycle no. 1, r/ w controlled timing (1,3,5,8) timing waveform of write cycle no. 2, ce controlled timing (1,3,5,8) notes: 1. r/ w or ce must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a low ce and a low r/ w for memory array writing cycle. 3. t wr is measured from the earlier of ce or r/ w (or sem or r/ w ) going high to the end of write cycle. 4. during this period, the i/o pins are in the output state and input signals must not be applied. 5. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last ce or r/ w . 7. timing depends on which enable signal is de-asserted first ce or r/ w . 8. if oe is low during r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 9. to access sram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . t ew must be met for either condition. r/ w t wc t hz t aw t wr t as t wp data out (2) t wz t dw t dh t ow oe address data in ce or sem (6) (4) (4) (3) 5668 drw 07 (7) (7) (9) 5668 drw 08 t wc t as t wr t dw t dh address data in ce or sem r/ w t aw t ew (3) (2) (6) (9)
10 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges preliminary timing waveform of semaphore read after write timing, either side (1) notes: 1. ce = v ih for the duration of the above timing (both write and read cycle). 2. ?data out valid? represents all i/o's (i/o 0 - i/o 7 ) equal to the semaphore value. timing waveform of semaphore write contention (1,3,4) notes: 1. d or = d ol = v il , ce r = ce l = v ih , semaphore flag is released from both sides (reads as ones from both sides) at cycle start. 2. ?a? may be either left or right port. ?b? is the opposite port from ?a?. 3. this parameter is measured from r/ w ?a? or sem ?a? going high to r/ w ?b? or sem ?b? going high. 4. if t sps is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtai n the flag. sem 5668 drw 09 t aw t ew t sop d ata 0 valid address t saa r/ w t wr t oh t ace valid address data in valid data out t dw t wp t dh t as t swrd t aoe t sop read cycle write cycle a 0 -a 2 oe valid (2) sem "a" 5668 drw 10 t sps match r/ w "a" match a 0"a" -a 2"a" side "a" (2) sem "b" r/ w "b" a 0"b" -a 2"b" side "b" (2) ,
6.42 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges 11 preliminary ac electrical characteristics over the operating temperature and supply voltage range 70t06/5l20 com'l only 70t06/5l25 com'l & ind symbol parameter min.max.min.max.unit busy timing (m/ s = v ih ) t baa busy access time from address match ____ 20 ____ 20 ns t bda busy disable time from address not matched ____ 20 ____ 20 ns t ba c busy access time from chip enable low ____ 20 ____ 20 ns t bdc busy disable time from chip enable high ____ 17 ____ 17 ns t ap s arbitration priority set-up time (2 ) 5 ____ 5 ____ ns t bdd busy disable to valid data (3) ____ 30 ____ 30 ns t wh write hold after busy (5) 15 ____ 17 ____ ns busy timing (m/ s = v il ) t wb busy input to write (4) 0 ____ 0 ____ ns t wh write hold after busy (5) 15 ____ 17 ____ ns port-to-port delay timing t wdd write pulse to data delay (1 ) ____ 45 ____ 50 ns t dd d write data valid to read data delay (1) ____ 35 ____ 35 ns 5668 tb l 1 3 notes: 1. port-to-port delay through sram cells from writing port to reading port, refer to "timing waveform of write port-to-port read and busy (m/ s = v ih )". 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of 0, t wdd ? t wp (actual) or t ddd ? t dw (actual). 4. to ensure that the write cycle is inhibited during contention. 5. to ensure that a write cycle is completed after contention. notes: 1. to ensure that the earlier of the two ports wins. t aps is ignored for m/ s = v il (slave). 2. ce l = ce r = v il 3. oe = v il for the reading port. 4. if m/ s = v il (slave) then busy is input. then for this example busy ?a? = v ih and busy ?b? input is shown above. 5. all timing is the same for left and right port. port "a" may be either left or right port. port "b" is the port opposite f rom port "a". 5668 drw 11 t dw t aps addr "a" t wc data out "b" match t wp r/w "a" data in "a" addr "b" t dh valid (1) match busy "b" t bda valid t bdd t ddd (3) t wdd t baa timing waveform of write port-to-port read and busy (2,4,5) (m/ s = v ih )
12 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges preliminary timing waveform of write with busy notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from ?a?. 2. if t aps is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. waveform of busy arbitration cycle controlled by address match timing (1) (m/ s = v ih ) waveform of busy arbitration controlled by ce timing (1) (m/ s = v ih ) notes: 1. t wh must be met for both busy input (slave) output master. 2. busy is asserted on port ?b? blocking r/ w ?b? , until busy ?b? goes high. 3. t wb is only for the slave version. 5668 drw 12 r/ w "a" busy "b" t wp t wb (3) r/ w "b" t wh (1) (2) , 5668 drw 13 addr "a" and "b" addresses match ce "a" ce "b" busy "b" t aps t bac t bdc (2) 5668 drw 14 addr "a" address "n" addr "b" busy "b" t aps t baa t bda (2) matching address "n"
6.42 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges 13 preliminary notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from ?a?. 2. see interrupt truth table iii. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. ac electrical characteristics over the operating temperature and supply voltage range 70t06/5l20 com'l only 70t06/5l25 com'l & ind symbol parameter min.max.min.max.unit interrupt timing t as address set-up time 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ ns t ins interrupt set time ____ 20 ____ 20 ns t inr interrupt reset time ____ 20 ____ 20 ns 5668 tbl 14 waveform of interrupt timing (1) 5668 drw 15 addr "a" interrupt set address ce "a" r/ w "a" t as t wc t wr (3) (4) t ins (3) i nt "b" (2) 5668 drw 16 addr "b" interrupt clear address ce "b" oe "b" t as t rc (3) t inr (3) i nt "b" (2)
14 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges preliminary truth table iii ? interrupt flag (1) notes: 1. assumes busy l = busy r = v ih . 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. a 13 is a nc for idt70t05, therefore interrupt addresses are 1fff and 1ffe. left port right port function r/ w l ce l oe l a 13l -a 0l int l r/ w r ce r oe r a 13r -a 0r int r l l x 3fff (4 ) xxxx x l (2 ) set rig ht int r flag xxxxxxll3fff (4) h (3 ) re set right int r flag xxx x l (3 ) llx3ffe (4) xset left int l flag x l l 3ffe (4 ) h (2 ) x x x x x reset left int l flag 5668 tbl 15 truth table v ? example of semaphore procurement sequence (1,2,3) notes: 1. this table denotes a sequence of events for only one of the eight semaphores on the idt70t06/5. 2. there are eight semaphore flags written to via i/o 0 and read from all i/o's (i/o 0 - i/o 7 ). these eight semaphores are addressed by a 0 -a 2 . 3. ce = v ih , sem = v il to access the semaphores. refer to the semaphore read/write control truth table. functions d 0 - d 7 left d 0 - d 7 right status no action 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token right port writes "0" to semaphore 0 1 no change. right side has no write access to semaphore left port writes "1" to semaphore 1 0 right port obtains semaphore token left port writes "0" to semaphore 1 0 no change. left port has no write access to semaphore right port writes "1" to semaphore 0 1 left port obtains semaphore token left port writes "1" to semaphore 1 1 semaphore free right port writes "0" to semaphore 1 0 right port has semaphore token right port writes "1" to semaphore 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token left port writes "1" to semaphore 1 1 semaphore free 5668 tbl 17 truth table iv ? address busy arbitration notes: 1. pins busy l and busy r are both outputs when the part is configured as a master. both are inputs when configured as a slave. busy x outputs on the idt70t06/5 are push pull, not open drain outputs. on slaves the busy x input internally inhibits writes. 2. l if the inputs to the opposite port were stable prior to the address and enable inputs of this port. h if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs cannot be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. inputs outputs function ce l ce r a 13l -a 0l (4) a 13r -a 0r busy l (1) busy r (1 ) x x no match h h normal h x match h h normal x h match h h normal l l match (2) (2) write inhibit (3) 5668 tbl 16 4. a 13 is a nc for idt70t05. address comparison will be for a 0 - a 12 .
6.42 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges 15 preliminary functional description the idt70t06/5 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt70t06/5 has an automatic power down feature controlled by ce . the ce controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce = v ih ). when a port is enabled, access to the entire memory array is permitted. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is set when the right port writes to memory location 3ffe (hex). the left port clears the interrupt by reading address location 3ffe. likewise, the right port interrupt flag ( int r ) is set when the left port writes to memory location 3fff (hex) (1ffe or 1fff for idt70t05) and to clear the interrupt flag ( int r ), the right port must read the memory location 3fff. the message (8 bits) at 3ffe or 3fff (1ffe or 1fff for idt70t05) is user-defined. if the interrupt function is not used, address locations 3ffe and 3fff (1ffe or 1fff for idt70t05) are not used as mail boxes, but as part of the random access memory. refer to truth table iii for the interrupt operation. busy logic busy logic provides a hardware indication that both ports of the sram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the sram is ?busy?. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applications. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. if the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the m/ s pin. once in slave mode the busy pin operates solely as a pin. normal operation can be programmed by tying the busy pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. the busy outputs on the idt 70t06/5 ram in master mode, are push-pull type outputs and do not require pull up resistors to operate. if these rams are being expanded in depth, then the busy indication for the resulting array requires the use of an external and gate. width expansion with busy logic master/slave arrays when expanding an idt70t06/5 sram array in width while using busy logic, one master part is used to decide which side of the sram array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master use the busy signal as a write inhibit signal. thus on the idt70t06/5 ram the busy pin is an output if the part is used as a master (m/ s pin = v ih ), and the busy pin is an input if the part used as a slave (m/ s pin = v il ) as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for part of the other word. the busy arbitration, on a master, is based on the chip enable and address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with the r/ w signal. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. semaphores the idt70t06/5 is an extremely fast dual-port 16/8k x 8 cmos static ram with an additional 8 address locations dedicated to binary semaphore flags. these flags allow either processor on the left or right side of the dual-port sram to claim a privilege over the other processor for functions defined by the system designer?s software. as an ex- ample, the semaphore can be used by one processor to inhibit the other from accessing a portion of the dual-port sram or any other shared figure 3. busy and chip enable routing for both width and depth expansion with idt70t06/5 srams. 5668 drw 17 master dual port sram busy (l) busy (r) ce master dual port sram busy (l) busy (r) ce slave dual port sram busy (l) busy (r) ce slave dual port sram busy (l) busy (r) ce busy (l) busy (r) d e c o d e r ,
16 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges preliminary standard static ram. each of the flags has a unique address which can be accessed by either side through address pins a 0 ? a 2 . when accessing the semaphores, none of the other address pins has any effect. when writing to a semaphore, only data pin d 0 is used. if a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see truth table v). that semaphore can now only be modified by the side showing the zero. when a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. the fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (a thor- ough discussion on the use of this feature follows shortly.) a zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. when a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. the read value is latched into one side?s output register when that side's semaphore select (sem) and output enable ( oe ) signals go active. this serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. because of this latch, a repeated read of a semaphore in a test loop must cause either signal ( sem or oe ) to go inactive or the output will never change. a sequence write/read must be used by the semaphore in order to guarantee that no system level contention will occur. a processor requests access to shared resources by attempting to write a zero into a semaphore location. if the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see table v). as an example, assume a processor writes a zero to the left port at a free semaphore location. on a subsequent read, the processor will verify that it has written success- fully to that location and will assume control over the resource in question. meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. had a sequence of read/write been used instead, system contention problems could have occurred during the gap between the read and write cycles. it is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. the reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in figure 4. two sema- phore request latches feed into a semaphore flag. whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. this condition will continue until a one is written to the same semaphore request latch. should the other side?s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side?s request latch. the second side?s flag will now stay low until its semaphore request latch is written to a one. from this it is easy to understand that, if a semaphore is requested and the processor which requested it no resource. the dual-port sram features a fast access time, and both ports are completely independent of each other. this means that the activity on the left port in no way slows the access time of the right port. both ports are identical in function to standard cmos static ram and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous read/write of, a non- semaphore location. semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the dual-port sram. these devices have an automatic power-down feature controlled by ce , the dual-port sram enable, and sem , the semaphore enable. the ce and sem pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. this is the condition which is shown in truth table i where ce and sem are both high. systems which can best use the idt70t06/5 contain multiple proces- sors or controllers and are typically very high-speed systems which are software controlled or software intensive. these systems can benefit from a performance increase offered by the idt70t06/5's hardware sema- phores, which provide a lockout mechanism without requiring complex programming. software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. the idt70t06/5 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. an advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. this can prove to be a major advantage in very high- speed systems. how the semaphore flags work the semaphore logic is a set of eight latches which are independent of the dual-port sram. these latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphores provide a hardware assist for a use assignment method called ?token passing allocation.? in this method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. if the left processor wants to use this resource, it requests the token by setting the latch. this processor then verifies its success in setting the latch by reading it. if it was successful, it assumes control over the shared resource. if it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. the left processor can then either repeatedly request that semaphore?s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. once the right side has relinquished the token, the left side should succeed in gaining control. the semaphore flags are active low. a token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. the eight semaphore flags reside within the idt70t06/5 in a separate memory space from the dual-port sram. this address space is accessed by placing a low input on the sem pin (which acts as a chip select for the semaphore flags) and using the other control pins (address, oe , and r/ w ) as they would be used in accessing a
6.42 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges 17 preliminary longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. the critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. the semaphore logic is specially designed to resolve this problem. if simultaneous requests are made, the logic guarantees that only one side receives the token. if one side is earlier than the other in making the request, the first side to make the request will receive the token. if both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. one caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. as with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. since any sema- phore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. using semaphores?some examples perhaps the simplest application of semaphores is their application as resource markers for the idt70t06/5?s dual-port sram. say the 16k x 8 sram was to be divided into two 8k x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. semaphore 0 could be used to indicate the side which would control the lower section of memory, and semaphore 1 could be defined as the indicator for the upper section of memory. to take a resource, in this example the lower 8k of dual-port sram, the processor on the left port could write and then read a zero in to semaphore 0. if this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 8k. meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into semaphore 0. at this point, the software could choose to try and gain control of the second 8k section by writing, then reading a zero into semaphore 1. if it succeeded in gaining control, it would lock out the left side. once the left side was finished with its task, it would write a one to semaphore 0 and may then try to gain access to semaphore 1. if semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into semaphore 1. if the right processor performs a similar task with semaphore 0, this protocol would allow the two processors to swap 8k blocks of dual-port sram with each other. the blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. all eight semaphores could be used to divide the dual-port sram or other shared resources into eight parts. semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. semaphores are a useful form of arbitration in systems like disk interfaces where the cpu must be locked out of a section of memory during a transfer and the i/o device cannot tolerate any wait states. with the use of semaphores, once the two devices has determined which memory area was ?off-limits? to the cpu, both the cpu and the i/ o devices could access their assigned portions of memory continuously without any wait states. semaphores are also useful in applications where no memory ?wait? state is available on one or both sides. once a semaphore handshake has been performed, both processors can access their assigned sram segments at full speed. another application is in the area of complex data structures. in this case, block arbitration is very important. for this application one processor may be responsible for building and updating a data structure. the other processor then reads and interprets that data structure. if the interpreting processor reads an incomplete data structure, a major error condition may exist. therefore, some sort of arbitration must be used between the two different processors. the building processor arbitrates for the block, locks it and then is able to go in and update the data structure. when the update is completed, the data structure block is released. this allows the interpreting processor to come back and read the complete data structure, thereby guaran- teeing a consistent data structure. d 0 5668 drw 18 d q write d 0 d q write semaphore request flip flop semaphore request flip flop lport rport semaphore read semaphore read , figure 4. idt70t06/5 semaphore logic
18 idt70t06/5l high-speed 2.5v 16/8k x 8 dual-port static ram industrial and commercial temperature ranges preliminary ordering information corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 08/15/02: initial public release 01/29/09: page 18 removed "idt" from orderable part number note: 1 . contact your local sales office for industrial temp range in other speeds, packages and powers. 5668 drw 19 pf bf 64-pin tqfp (pn64-1) 100-pin fpbga (bf100) 20 25 l low power 128k (16k x 8-bit) 2.5v dual-port ram 64k (8k x 8-bit) 2.5v dual-port ram 70t06 70t05 speed in nanosecond s commercial only commercial & industrial a power 999 speed a package xxxxx device type process/ temperature range blank i (1) commercial (0c to +70c) industrial (-40c to +85c) a preliminary datasheet: definition "preliminary' datasheets contain descriptions for products that are in early release.

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